35 search results - page 1 / 7 » Loop Scheduling and Partitions for Hiding Memory Latencies |
ISSS
1999
IEEE
14 years 3 months ago
1999
IEEE
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is...
ICPADS
2006
IEEE
14 years 4 months ago
2006
IEEE
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
TECS
2010
13 years 9 months ago
2010
CASES
2001
ACM
14 years 2 months ago
2001
ACM
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
ISCA
1992
IEEE
14 years 2 months ago
1992
IEEE