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MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
13 years 11 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
13 years 11 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
ECRTS
2010
IEEE
13 years 8 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
TVLSI
2008
157views more  TVLSI 2008»
13 years 7 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
TPDS
2002
104views more  TPDS 2002»
13 years 7 months ago
Performance Guarantees for Web Server End-Systems: A Control-Theoretical Approach
The Internet is undergoing substantial changes from a communication and browsing infrastructure to a medium for conducting business and marketing a myriad of services. The World W...
Tarek F. Abdelzaher, Kang G. Shin, Nina T. Bhatti