Sciweavers

706 search results - page 64 / 142
» Loop Scheduling for Heterogeneity
Sort
View
ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
14 years 28 days ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...
JISE
2002
165views more  JISE 2002»
13 years 8 months ago
Locality-Preserving Dynamic Load Balancing for Data-Parallel Applications on Distributed-Memory Multiprocessors
Load balancing and data locality are the two most important factors in the performance of parallel programs on distributed-memory multiprocessors. A good balancing scheme should e...
Pangfeng Liu, Jan-Jan Wu, Chih-Hsuae Yang
TWC
2010
13 years 3 months ago
Optimized opportunistic multicast scheduling (OMS) over wireless cellular networks
Optimized opportunistic multicast scheduling (OMS) is studied for cellular networks, where the problem of efficiently transmitting a common set of fountain-encoded data from a sin...
Tze-Ping Low, Man-On Pun, Yao-Win Peter Hong, C.-C...
ICFP
2008
ACM
14 years 8 months ago
A scheduling framework for general-purpose parallel languages
The trend in microprocessor design toward multicore and manycore processors means that future performance gains in software will largely come from harnessing parallelism. To reali...
Matthew Fluet, Mike Rainey, John H. Reppy
ISPAN
2005
IEEE
14 years 2 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg