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ISCAS
2008
IEEE
101views Hardware» more  ISCAS 2008»
16 years 16 days ago
Digitally enhanced analog circuits: System aspects
— An overview of digital enhancement techniques for analog circuits is presented. Recent research suggests that the high density and low energy of digital circuits can be leverag...
Boris Murmann, Christian Vogel, Heinz Koeppl
USENIX
2003
15 years 7 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
FGIT
2009
Springer
16 years 21 days ago
Predicting the Performance of a GRID Environment: An Initial Effort to Increase Scheduling Efficiency
GRID environments are privileged targets for computation-intensive problem solving in areas from weather forecasting to seismic analysis. Mainly composed by commodity hardware, th...
Nuno Guerreiro, Orlando Belo
DFT
2007
IEEE
103views VLSI» more  DFT 2007»
16 years 14 days ago
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
Avijit Dutta, Nur A. Touba
163
Voted
ISLPED
2007
ACM
123views Hardware» more  ISLPED 2007»
15 years 7 months ago
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
We address power minimization of earliest deadline first and ratemonotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+ ) f...
Sushu Zhang, Karam S. Chatha, Goran Konjevod