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» Low Power Hardware for a High Performance PDA
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FPL
2008
Springer
119views Hardware» more  FPL 2008»
15 years 7 months ago
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
Jan de Cuveland, Felix Rettig, Venelin Angelov, Vo...
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
16 years 6 days ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam
177
Voted
CLUSTER
2007
IEEE
15 years 10 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
15 years 11 months ago
Dynamic power management using on demand paging for networked embedded systems
— The power consumption of the network interface plays a major role in determining the total operating lifetime of wireless networked embedded systems. In case of on-demand pagin...
Yuvraj Agarwal, Curt Schurgers, Rajesh Gupta
127
Voted
ICIP
2009
IEEE
16 years 7 months ago
A High Throughput Cabac Algorithm Using Syntax Element Partitioning
Enabling parallel processing is becoming increasingly necessary for video decoding as performance requirements continue to rise due to growing resolution and frame rate demands. I...