1307 search results - page 110 / 262 » Low Power Hardware for a High Performance PDA |
174
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ICC
2008
IEEE
16 years 18 days ago
2008
IEEE
— We consider relaying strategies for two-way relay channels, where two terminals transmits simultaneously to each other with the help of relays. A memoryless system is considere...
158
Voted
SAMOS
2007
Springer
16 years 8 days ago
2007
Springer
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
187
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
Abstract—In low bit-rate video communication, temporal subsampling is usually used due to limited available bandwidth. Motion compensated frame interpolation (MCFI) techniques ar...
168
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ICDCS
2005
IEEE
15 years 11 months ago
2005
IEEE
Power heterogeneous ad hoc networks are characterized by link layer asymmetry: the ability of lower power nodes to receive transmissions from higher power nodes but not vice versa...
159
Voted
MICRO
2009
IEEE
16 years 24 days ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...