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ISLPED
1997
ACM
99views Hardware» more  ISLPED 1997»
13 years 11 months ago
Low power data processing by elimination of redundant computations
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is...
Mir Azam, Paul D. Franzon, Wentai Liu
CODES
2009
IEEE
14 years 2 months ago
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redun...
Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
13 years 11 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
ISCAS
2007
IEEE
107views Hardware» more  ISCAS 2007»
14 years 1 months ago
Low power variable block size motion estimation using pixel truncation
— This paper presents a method of low-power variable-block-size motion estimation using pixel truncation. Previous work focused on implementing pixel truncation using fixed-bloc...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan