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ICES
2010
Springer
277views Hardware» more  ICES 2010»
13 years 5 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
AUTOID
2005
IEEE
14 years 1 months ago
A Low Power and High Performance Analog Front End for Passive RFID Transponder
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, amo...
Jianyun Hu, Hao Min
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
14 years 7 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
JCP
2008
324views more  JCP 2008»
13 years 7 months ago
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
Keivan Navi, Omid Kavehie, Mahnoush Rouholamini, A...
IPPS
2005
IEEE
14 years 1 months ago
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...
Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sat...