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» Low Power Testing of VLSI Circuits: Problems and Solutions
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ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Register placement for low power clock network
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...
ISPD
2005
ACM
188views Hardware» more  ISPD 2005»
14 years 1 months ago
A semi-persistent clustering technique for VLSI circuit placement
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant p...
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, S...
VLSISP
2010
148views more  VLSISP 2010»
13 years 6 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
DAC
1999
ACM
14 years 8 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
14 years 26 days ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi