240 search results - page 14 / 48 » Low energy asynchronous architectures |
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Low energy and small switch area usage are two of the important design objectives in FPGA global routing architecture design. This paper presents an improved MCF model based CAD ...
CAMP
2005
IEEE
14 years 1 months ago
2005
IEEE
— In this paper, a programmable analog retina is presented and compared with state of the art MPU for embedded imaging applications. The comparison is based on the energy require...
ISCAPDCS
2008
13 years 9 months ago
2008
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges i...
ASYNC
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...