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» Low power architecture of the soft-output Viterbi algorithm
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ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
13 years 11 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
OSDI
2008
ACM
14 years 7 months ago
Greening the Switch
Active research is being conducted in reducing power consumption of all the components of the Internet. To that end, we propose schemes for power reduction in network switches - T...
Ganesh Ananthanarayanan, Randy H. Katz
DAC
2009
ACM
14 years 8 months ago
Power modeling of graphical user interfaces on OLED displays
Emerging organic light-emitting diode (OLED)-based displays obviate external lighting; and consume drastically different power when displaying different colors, due to their emiss...
Mian Dong, Yung-Seok Kevin Choi, Lin Zhong
DAC
2008
ACM
14 years 8 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2007
ACM
14 years 8 months ago
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Behnam Amelifard, Massoud Pedram