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ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
CASES
2004
ACM
14 years 24 days ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 7 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
ISCAS
2003
IEEE
79views Hardware» more  ISCAS 2003»
14 years 19 days ago
Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder
A new design of Psycho-Acoustic Model in MPEG-214 AAC encoding is proposed. Differing from the conventional PC-based and DSP-based encoders, it was based on hybrid architectures. ...
Tsung-Han Tsai, Shih-Way Huang, Liang-Gee Chen
ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
14 years 4 months ago
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Du...