331 search results - page 12 / 67 » Low power implementation of a turbo-decoder on programmable ... |
232
click to vote
CVPR
2011
IEEE
15 years 1 months ago
2011
IEEE
We describe an imaging architecture for compressive video sensing termed programmable pixel compressive camera (P2C2). P2C2 allows us to capture fast phenomena at frame rates high...
145
click to vote
ICPP
1991
IEEE
15 years 9 months ago
1991
IEEE
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
148
click to vote
DATE
2007
IEEE
16 years 4 days ago
2007
IEEE
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
175
Voted
HIPEAC
2009
Springer
16 years 17 days ago
2009
Springer
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
154
click to vote
IJNSEC
2007
15 years 5 months ago
2007
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...