331 search results - page 42 / 67 » Low power implementation of a turbo-decoder on programmable ... |
261
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ECCTD
2011
14 years 5 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
173
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ARCS
2009
Springer
16 years 13 days ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
142
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
169
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ISCA
2002
IEEE
15 years 10 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
153
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ACSAC
2005
IEEE
15 years 11 months ago
2005
IEEE
Logging and auditing is an important system facility for monitoring correct system operation and for detecting potential security problems. We present an architecture for implemen...