97 search results - page 18 / 20 » Low power network processor design using clock gating |
127
click to vote
EUROPAR
2005
Springer
15 years 8 months ago
2005
Springer
Abstract. Blue Gene/L uses a large number of low power processors, together with multiple integrated interconnection networks, to build a supercomputer with low cost, space and pow...
149
click to vote
JSA
2010
14 years 10 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
143
click to vote
ESAS
2004
Springer
15 years 8 months ago
2004
Springer
The common perception of public key cryptography is that it is complex, slow and power hungry, and as such not at all suitable for use in ultra-low power environments like wireless...
135
Voted
SC
2004
ACM
15 years 8 months ago
2004
ACM
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
147
Voted
TVLSI
2010
14 years 9 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...