TVLSI 2010 - PDF Preprint Papers

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TVLSI
2010

345views Artificial Intelligence» more TVLSI 2010»

Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding

13 years 7 months ago

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By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...

Shu Li, Tong Zhang

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Id	Views	Title	Status

1	345	Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding	claim
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3	299	Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods	claim
4	262	C-Pack: A High-Performance Microprocessor Cache Compression Algorithm	claim
5	223	A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors	claim
6	206	Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis	claim
7	204	Improving FPGA Performance for Carry-Save Arithmetic	claim
8	203	LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization	claim
9	200	A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates	claim
10	199	Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment	claim
11	195	Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage	claim
12	179	Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors	claim
13	176	Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs	claim
14	175	A Low-Power DSP for Wireless Communications	claim
15	168	Variation-Aware System-Level Power Analysis	claim
16	164	Design and Implementation of a Sort-Free K-Best Sphere Decoder	claim
17	159	SRAM Read/Write Margin Enhancements Using FinFETs	claim
18	157	Asynchronous Current Mode Serial Communication	claim
19	157	Low-Power Multimedia System Design by Aggressive Voltage Scaling	claim
20	154	Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters	claim
21	153	Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs	claim
22	149	On the Power Management of Simultaneous Multithreading Processors	claim
23	149	A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization	claim
24	149	Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks	claim
25	140	Pattern Sensitive Placement Perturbation for Manufacturability	claim
26	138	Asynchronous Data-Driven Circuit Synthesis	claim
27	135	Accurate Predictive Interconnect Modeling for System-Level Design	claim
28	126	Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling	claim
29	123	Resource Based Optimization for Simultaneous Shield and Repeater Insertion	claim
30	111	X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing	claim
31	89	Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization	claim

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