97 search results - page 4 / 20 » Low power network processor design using clock gating |
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
ISPASS
2005
IEEE
14 years 1 months ago
2005
IEEE
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...