62 search results - page 12 / 13 » Low-latency scheduling in large switches |
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
SP
1999
IEEE
14 years 2 months ago
1999
IEEE
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design ...
SPAA
1997
ACM
14 years 2 months ago
1997
ACM
- Multithreading aims to tolerate latency by overlapping communication with computation. This report explicates the multithreading capabilities of the EM-X distributed-memory multi...
ASPDAC
2005
ACM
14 years 3 months ago
2005
ACM
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
IPPS
2009
IEEE
14 years 4 months ago
2009
IEEE
Various studies have shown that OS jitter can degrade parallel program performance considerably at large processor counts. Most sources of system jitter fall broadly into 5 catego...