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» Lower Bounds on Correction Networks
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FPL
2004
Springer
114views Hardware» more  FPL 2004»
15 years 11 months ago
Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA
Several implementations of Artificial Neural Networks have been reported in scientific papers. Nevertheless, these implementations do not allow the direct use of off-line trained n...
Pedro Ferreira, Pedro Ribeiro, Ana Antunes, Fernan...
ICNS
2006
IEEE
16 years 6 days ago
MojaveComm: A Robust Group Communication Library for Grid Environments
This paper introduces a fault-tolerant group communication protocol that is aimed at grid and wide area environments. The protocol has two layers. The lower layer provides a total...
Cristian Tapus, David A. Noblet, Jason Hickey
DAC
1997
ACM
15 years 10 months ago
More Practical Bounded-Skew Clock Routing
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
Andrew B. Kahng, Chung-Wen Albert Tsao
STOC
1993
ACM
141views Algorithms» more  STOC 1993»
15 years 10 months ago
Bounds for the computational power and learning complexity of analog neural nets
Abstract. It is shown that high-order feedforward neural nets of constant depth with piecewisepolynomial activation functions and arbitrary real weights can be simulated for Boolea...
Wolfgang Maass
APPROX
2008
Springer
190views Algorithms» more  APPROX 2008»
15 years 8 months ago
The Complexity of Local List Decoding
We study the complexity of locally list-decoding binary error correcting codes with good parameters (that are polynomially related to information theoretic bounds). We show that co...
Dan Gutfreund, Guy N. Rothblum