139 search results - page 10 / 28 » MB : An Integrated Architecture for Pervasive Computing and... |
DAC
2004
ACM
13 years 11 months ago
2004
ACM
A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an effic...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
WOA
2003
13 years 9 months ago
2003
— Pervasive and ubiquitous computing is enabling the implementation of “smart environments”, i.e., environments where applications support and enhance the abilities of their ...
ARITH
2001
IEEE
13 years 11 months ago
2001
IEEE
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
BIRTHDAY
2006
Springer
13 years 11 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...