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TVLSI
2008
120views more  TVLSI 2008»
13 years 10 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
CCR
2007
85views more  CCR 2007»
13 years 10 months ago
Don't optimize existing protocols, design optimizable protocols
As networks grow in size and complexity, network management has become an increasingly challenging task. Many protocols have tunable parameters, and optimization is the process of...
Jiayue He, Jennifer Rexford, Mung Chiang
FSTTCS
2008
Springer
13 years 11 months ago
Runtime Monitoring of Metric First-order Temporal Properties
ABSTRACT. We introduce a novel approach to the runtime monitoring of complex system properties. In particular, we present an online algorithm for a safety fragment of metric first...
David A. Basin, Felix Klaedtke, Samuel Müller...
SASP
2008
IEEE
140views Hardware» more  SASP 2008»
14 years 4 months ago
An FPGA Design Space Exploration Tool for Matrix Inversion Architectures
— Matrix inversion is a common function found in many algorithms used in wireless communication systems. As FPGAs become an increasingly attractive platform for wireless communic...
Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan ...
DAC
2002
ACM
14 years 11 months ago
Compiler-directed scratch pad memory hierarchy design and management
One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly impo...
Mahmut T. Kandemir, Alok N. Choudhary