36 search results - page 4 / 8 » MFAST: a single chip highly parallel image processing archit... |
EUROPAR
2009
Springer
14 years 2 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
NETWORKING
2007
13 years 8 months ago
2007
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A funda...
RSP
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...