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FPL
2006
Springer
108views Hardware» more  FPL 2006»
13 years 11 months ago
Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
James Moscola, Young H. Cho, John W. Lockwood
CAINE
2006
13 years 9 months ago
A novel parallel hardware and software solution for a large-scale biologically realistic cortical simulation
This research addresses a major gap in our conceptual understanding of synaptic and brain-like network dynamics. Over the course of several years we have designed and implemented ...
Frederick C. Harris Jr., Mark C. Ballew, Jason Bau...
CLUSTER
2011
IEEE
12 years 7 months ago
Dynamic Load Balance for Optimized Message Logging in Fault Tolerant HPC Applications
—Computing systems will grow significantly larger in the near future to satisfy the needs of computational scientists in areas like climate modeling, biophysics and cosmology. S...
Esteban Meneses, Laxmikant V. Kalé, Greg Br...
KDD
2005
ACM
170views Data Mining» more  KDD 2005»
14 years 8 months ago
Parallel mining of closed sequential patterns
Discovery of sequential patterns is an essential data mining task with broad applications. Among several variations of sequential patterns, closed sequential pattern is the most u...
Shengnan Cong, Jiawei Han, David A. Padua
APCSAC
2006
IEEE
14 years 1 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...