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JWSR
2008
109views more  JWSR 2008»
13 years 8 months ago
DsCWeaver: Synchronization-Constraint Aspect Extension to Procedural Process Specification Languages
BPEL is emerging as an open-standards language for Web service composition. However, its procedural style can lead to inflexible and tangled code for managing a crosscutting aspec...
Qinyi Wu, Calton Pu, Akhil Sahai, Roger S. Barga
JSS
2006
104views more  JSS 2006»
13 years 8 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
INTEGRATION
2007
98views more  INTEGRATION 2007»
13 years 8 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
ISCI
2007
82views more  ISCI 2007»
13 years 8 months ago
Managing software process measurement: A metamodel-based approach
The evaluation of software processes is nowadays a very important issue due to the growing interest of software companies in the improvement of the productivity and quality of del...
Francisco García, Manuel A. Serrano, Jos&ea...
TPDS
2008
89views more  TPDS 2008»
13 years 8 months ago
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...