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IPPS
2005
IEEE
14 years 3 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 3 months ago
HIBI-based multiprocessor SoC on FPGA
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
ISPAN
2005
IEEE
14 years 3 months ago
An FPGA-Based Floating-Point Jacobi Iterative Solver
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
Gerald R. Morris, Viktor K. Prasanna
ISQED
2005
IEEE
106views Hardware» more  ISQED 2005»
14 years 3 months ago
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael ...
ISQED
2005
IEEE
119views Hardware» more  ISQED 2005»
14 years 3 months ago
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. In this paper, we present a fa...
Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, ...