Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...
Thorsten Jungeblut, Ralf Dreesen, Mario Porrmann, ...
Since the non-cache parts of a core are less regular, compared to on-chip caches, tolerating manufacturing defects in the processing core is a more challenging problem. Due to the ...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the timeconsuming analysis of radio-frequency/millimeter-wave (RF/ MM) int...
Xuexin Liu, Hao Yu, Jacob Relles, Sheldon X.-D. Ta...
Database appliances offer fully integrated hardware, storage, operating system, database, and related software in a single package. Database appliances have a relatively long hist...
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
Abid Rafique, Nachiket Kapre, George A. Constantin...