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» Mach on a Virtually Addressed Cache Architecture
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MACH
1990
13 years 8 months ago
Mach on a Virtually Addressed Cache Architecture
Chia Chao, Milon Mackey, Bart Sears
CLUSTER
2008
IEEE
14 years 2 months ago
Context-aware address translation for high performance SMP cluster system
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
Moon-Sang Lee, Joonwon Lee, Seungryoul Maeng
LCTRTS
2009
Springer
14 years 2 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...
ECOOP
1998
Springer
13 years 12 months ago
Object-Oriented Architectural Support for a Java Processor
In this paper, we propose architectural support for object manipulation, stack processing and method invocation to enhance the execution speed of Java bytecodes. First, a virtual a...
Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gade...
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 1 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu