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ISPASS
2003
IEEE
14 years 2 months ago
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that ...
John W. Haskins Jr., Kevin Skadron
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 2 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
MICRO
2003
IEEE
128views Hardware» more  MICRO 2003»
14 years 2 months ago
IPStash: a Power-Efficient Memory Architecture for IP-lookup
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
Stefanos Kaxiras, Georgios Keramidas
SBACPAD
2003
IEEE
120views Hardware» more  SBACPAD 2003»
14 years 2 months ago
Comparison of Genomes Using High-Performance Parallel Computing
Comparison of the DNA sequences and genes of two genomes can be useful to investigate the common functionalities of the corresponding organisms and get a better understanding of h...
Nalvo F. Almeida Jr., Carlos E. R. Alves, Edson C&...
CHI
2003
ACM
14 years 2 months ago
Breakingstory: visualizing change in online news
BreakingStory is an interactive system for visualizing change in online news. The system regularly collects the text from the front pages of international daily news web sites. It...
Jean Anne Fitzpatrick, James Reffell, Moryma Aydel...