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» Mapping Computation with No Memory
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ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
15 years 8 months ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski
CORR
2006
Springer
116views Education» more  CORR 2006»
15 years 3 months ago
Memory Aware High-Level Synthesis for Embedded Systems
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
Gwenolé Corre, Eric Senn, Nathalie Julien, ...
IBPRIA
2007
Springer
15 years 9 months ago
Invariant Multi-scale Object Categorisation and Recognition
Object recognition requires that templates with canonical views are stored in memory. Such templates must somehow be normalised. In this paper we present a novel method for obtaini...
João Rodrigues, J. M. Hans du Buf
ICPP
2008
IEEE
15 years 9 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
IPPS
1996
IEEE
15 years 7 months ago
How to Optimize Residual Communications?
Minimizing communications when mapping affine loop nests onto distributed memory parallel computers has already drawn a lot of attention. This paper focuses on the next step: as i...
Michèle Dion, Cyril Randriamaro, Yves Rober...