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» Mapping Interconnection Networks into VEDIC Networks
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ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
14 years 4 months ago
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
Santithorn Bunchua, D. Scott Wills, Linda M. Wills
IDT
2007
96views more  IDT 2007»
13 years 7 months ago
Fuzzy cognitive network: A general framework
In this paper, we present a general computational and operational framework for the Fuzzy Cognitive Network (FCN), which is a direct extension of Fuzzy Cognitive Maps (FCM). The pr...
Theodoros L. Kottas, Yiannis S. Boutalis, Manolis ...
ISICT
2003
13 years 9 months ago
Topic maps for context management
Abstract. The advent of context-aware computing requires a new paradigm in information management. Context information in a computing environment will take the form of disparate an...
Ruaidhri Power
FPGA
2008
ACM
151views FPGA» more  FPGA 2008»
13 years 9 months ago
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
Michael T. Frederick, Arun K. Somani
TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias