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TCAD
2010
124views more  TCAD 2010»
13 years 2 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
DAC
1997
ACM
13 years 11 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
IPPS
2007
IEEE
14 years 1 months ago
An Architectural Framework for Automated Streaming Kernel Selection
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
CC
2008
Springer
144views System Software» more  CC 2008»
13 years 9 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
IPPS
2009
IEEE
14 years 2 months ago
Resource allocation strategies for constructive in-network stream processing
We consider the operator mapping problem for in-network stream processing, i.e., the application of a tree of operators in steady-state to multiple data objects that are continuou...
Anne Benoit, Henri Casanova, Veronika Rehn-Sonigo,...