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CODES
2011
IEEE
12 years 7 months ago
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
Benny Akesson, Po-Chun Huang, Fabien Clermidy, Den...
VTC
2010
IEEE
163views Communications» more  VTC 2010»
13 years 6 months ago
An ARQ Mechanism with Rate Control for Two-Hop Relaying Systems
— Wireless multi-hop relaying has been attracting considerable attention as a promising technique for future communication systems. The multi-hop relaying technique has many bene...
Soo-Yong Jeon, Dong-Ho Cho
WINET
2010
180views more  WINET 2010»
13 years 6 months ago
An analytical model for performance evaluation of multimedia applications over EDCA in an IEEE 802.11e WLAN
—We extend the modeling heuristic of [1] to evaluate the performance of an IEEE 802.11e infrastructure network carrying packet telephone calls, streaming video sessions and TCP c...
Sri Harsha, Anurag Kumar, Vinod Sharma
BMCBI
2005
152views more  BMCBI 2005»
13 years 7 months ago
Improved profile HMM performance by assessment of critical algorithmic features in SAM and HMMER
Background: Profile hidden Markov model (HMM) techniques are among the most powerful methods for protein homology detection. Yet, the critical features for successful modelling ar...
Markus Wistrand, Erik L. L. Sonnhammer
DSN
2009
IEEE
14 years 2 months ago
MAP-AMVA: Approximate mean value analysis of bursty systems
MAP queueing networks are recently proposed models for performance assessment of enterprise systems, such as multi-tier applications, where workloads are significantly affected b...
Giuliano Casale, Evgenia Smirni