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» Massively parallel processing on a chip
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CF
2007
ACM
13 years 11 months ago
Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations
We propose an application specific processor for computational quantum chemistry. The kernel of interest is the computation of electron repulsion integrals (ERIs), which vary in c...
Tirath Ramdas, Gregory K. Egan, David Abramson, Ki...
ISSS
2002
IEEE
138views Hardware» more  ISSS 2002»
14 years 13 days ago
An Object-Oriented Design Process for System-on-Chip Using UML
The object-oriented design process has been a hot topic in software development since it will improve product quality and productivity significantly, which is also a major issue i...
Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya ...
HPCA
2012
IEEE
12 years 3 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
HPCA
2002
IEEE
14 years 7 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...
ICPPW
2006
IEEE
14 years 1 months ago
Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
Sam Sander, Linda M. Wills