391 search results - page 18 / 79 » Massively parallel processing on a chip |
CISIS
2008
IEEE
14 years 2 months ago
2008
IEEE
The new era of multi-core processing challenges software designers to efficiently exploit the parallelism that is now massively available. Programmers have to exchange the conven...
WWW
2009
ACM
14 years 8 months ago
2009
ACM
Web search engines are facing formidable performance challenges as they need to process thousands of queries per second over billions of documents. To deal with this heavy workloa...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Model order reduction is an efficient technique to reduce the system complexity while producing a good approximation of the input-output behavior. However, the efficiency of reduc...
JPDC
2006
13 years 7 months ago
2006
The rapid development of space and computer technologies has made possible to store a large amount of remotely sensed image data, collected from heterogeneous sources. In particul...
MVA
1992
13 years 8 months ago
1992
This paper presents the design of an ASIC intended for optimal edge detection of blurred and noisy 2-D images. The chip has a parallel and pipelined architecture which processes a...