391 search results - page 23 / 79 » Massively parallel processing on a chip |
DGCI
2005
Springer
14 years 1 months ago
2005
Springer
Due to the restriction of SIMD mode to local operations in VLSI massively parallel vision chips, using programmable connections and asynchronous communications are key ingredients ...
PDP
2011
IEEE
12 years 11 months ago
2011
IEEE
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
ASAP
2011
IEEE
2011
IEEE
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
12 years 7 months ago
—To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleav...
IPPS
1996
IEEE
13 years 11 months ago
1996
IEEE
This paper presents the design and implementation of a Sliding Memory Plane (SliM) Array Processor, a mesh-connected SIMD architecture. To build the array processor, we developed ...
FPL
2004
Springer
14 years 28 days ago
2004
Springer
Abstract. In this paper, a novel architecture dedicated to image processing is presented. The most original aspect of the approach is the use of a System On Chip implemented in a F...