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» Massively parallel processing on a chip
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ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
13 years 12 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
CLUSTER
2008
IEEE
13 years 7 months ago
Benchmarking the effects of operating system interference on extreme-scale parallel machines
We investigate operating system noise, which we identify as one of the main reasons for a lack of synchronicity in parallel applications. Using a microbenchmark, we measure the no...
Peter H. Beckman, Kamil Iskra, Kazutomo Yoshii, Su...
HPCA
2000
IEEE
13 years 12 months ago
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620
The paper presents PowerMANNA - a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophi...
Peter M. Behr, S. Pletner, Angela C. Sodan
CLUSTER
2007
IEEE
14 years 1 months ago
Sequential and parallel implementation of a constraint-based algorithm for searching protein structures
— Data mining in biological structure libraries can be a powerful tool to better understand biochemical processes. This article introduces the LISA algorithm which enables the re...
Sascha Hunold, Thomas Rauber, Georg Wille
TVCG
2012
179views Hardware» more  TVCG 2012»
11 years 10 months ago
Parallel Computation of 2D Morse-Smale Complexes
—The Morse-Smale complex is a useful topological data structure for the analysis and visualization of scalar data. This paper describes an algorithm that processes all mesh eleme...
Nithin Shivashankar, Senthilnathan M, Vijay Natara...