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» Massively parallel processing on a chip
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IPPS
1997
IEEE
13 years 12 months ago
Modeling Compiled Communication Costs in Multiplexed Optical Networks
Improvements in optical technology will enable the constructionof high bandwidth, low latencyswitching networks. These networks have many applications in massively parallel proces...
Charles A. Salisbury, Rami G. Melhem
HICSS
1994
IEEE
127views Biometrics» more  HICSS 1994»
13 years 11 months ago
Angel: Resource Unification in a.64-bit Microkernel
The appearance of 64-bit processors allows a new approach to microkernel desagn From our experience with a message passang microkernel MESHIX, we discovered that a multi-address s...
Kevin Murray, Tim Wilkinson, Tom Stiemerling, Paul...
CLUSTER
2006
IEEE
13 years 11 months ago
Efficient Data-Movement for Lightweight I/O
Efficient data movement is an important part of any highperformance I/O system, but it is especially critical for the current and next-generation of massively parallel processing ...
Ron Oldfield, Patrick Widener, Arthur B. Maccabe, ...
CGO
2006
IEEE
14 years 1 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
HPCA
2009
IEEE
14 years 2 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes