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» Massively parallel processing on a chip
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HIS
2001
13 years 9 months ago
A Bayesian Track-before-Detect Algorithm for IR Point Target Detection
An algorithm has been developed for the detection of point targets in uncluttered background based on a Bayesian track before detect method. The algorithm has an application in th...
Robert C. Warren
IJHPCA
2006
117views more  IJHPCA 2006»
13 years 7 months ago
Recent Developments in Gridsolve
The purpose of GridSolve is to create the middleware necessary to provide a seamless bridge between the simple, standard programming interfaces and desktop systems that dominate t...
Asim YarKhan, Keith Seymour, Kiran Sagi, Zhiao Shi...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 1 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
IPPS
2006
IEEE
14 years 1 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
CLUSTER
2011
IEEE
12 years 7 months ago
Dynamic Load Balance for Optimized Message Logging in Fault Tolerant HPC Applications
—Computing systems will grow significantly larger in the near future to satisfy the needs of computational scientists in areas like climate modeling, biophysics and cosmology. S...
Esteban Meneses, Laxmikant V. Kalé, Greg Br...