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» Massively parallel processing on a chip
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DAC
1994
ACM
13 years 11 months ago
Acyclic Multi-Way Partitioning of Boolean Networks
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
Jason Cong, Zheng Li, Rajive Bagrodia
IJRR
2007
89views more  IJRR 2007»
13 years 7 months ago
Towards an Embedded Visuo-Inertial Smart Sensor
In neurological system of primates, changes in posture are detected by the central nervous system through a vestibular process. This process, located in inner ear, coordinates seve...
Pierre Chalimbaud, François Marmoiton, Fran...
INFOCOM
2007
IEEE
14 years 2 months ago
TriBiCa: Trie Bitmap Content Analyzer for High-Speed Network Intrusion Detection
Abstract—Deep packet inspection (DPI) is often used in network intrusion detection and prevention systems (NIDPS), where incoming packet payloads are compared against known attac...
N. Sertac Artan, H. Jonathan Chao
CASES
2008
ACM
13 years 9 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
SIGMOD
2007
ACM
179views Database» more  SIGMOD 2007»
14 years 7 months ago
How to barter bits for chronons: compression and bandwidth trade offs for database scans
Two trends are converging to make the CPU cost of a table scan a more important component of database performance. First, table scans are becoming a larger fraction of the query p...
Allison L. Holloway, Vijayshankar Raman, Garret Sw...