391 search results - page 71 / 79 » Massively parallel processing on a chip |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— We designed a high-efficiency class-E switchedmode power amplifier for a wireless networked micro-sensors system. In this system, where each sensor operates using a mic...
DNA
2001
Springer
14 years 6 days ago
2001
Springer
In the universal DNA chip method, target RNAs are mapped onto a set of DNA tags. Parallel hybridization of these tags with an indexed, complementary antitag array then provides an ...
ARCS
2006
Springer
13 years 11 months ago
2006
Springer
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this p...