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» Maurer computers for pipelined instruction processing
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IPPS
2005
IEEE
14 years 1 months ago
Effective Instruction Prefetching via Fetch Prestaging
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
Ayose Falcón, Alex Ramírez, Mateo Va...
IPPS
2006
IEEE
14 years 1 months ago
A code motion technique for accelerating general-purpose computation on the GPU
Recently, graphics processing units (GPUs) are providing increasingly higher performance with programmable internal processors, namely vertex processors (VPs) and fragment process...
T. Ikeda, Fumihiko Ino, Kenichi Hagihara
SIGUCCS
2003
ACM
14 years 21 days ago
Instructional support at small universities: a training perspective
This paper intends to present the challenges and opportunities encountered in technology training at small institutions using Trinity University as a case in point. During the cou...
Vidya Ananthanarayanan, Judith Reiffert
IEEEPACT
2003
IEEE
14 years 22 days ago
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjee...
DSN
2004
IEEE
13 years 11 months ago
An Architectural Framework for Providing Reliability and Security Support
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...