164 search results - page 7 / 33 » Measuring performance, power, and temperature from real proc... |
CLUSTER
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a feasibility study of a power-reduction scheme that reduces the thermal power of processors by lowering frequency and voltage in the context of high-performance comput...
ISCAPDCS
2001
13 years 9 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
MICRO
2012
IEEE
11 years 10 months ago
2012
IEEE
The past 10 years have delivered two significant revolutions. (1) Microprocessor design has been transformed by the limits of chip power, wire latency, and Dennard scaling—leadi...
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
We describe and evaluate two new, independently-applicable power reduction techniques for power management on processors that support dynamic voltage and frequency scaling (DVFS):...
SIGMOD
2008
ACM
14 years 8 months ago
2008
ACM
Many scientific, financial, data mining and sensor network applications need to work with continuous, rather than discrete data e.g., temperature as a function of location, or sto...