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» Measuring the Architecture Design Process
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CODES
2003
IEEE
14 years 4 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
ICCAD
2007
IEEE
151views Hardware» more  ICCAD 2007»
14 years 3 months ago
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
Cyrille Chavet, Caaliph Andriamisaina, Philippe Co...
SSPR
2000
Springer
14 years 2 months ago
A Framework for Classifier Fusion: Is It Still Needed?
We consider the problem and issues of classifier fusion and discuss how they should be reflected in the fusion system architecture. We adopt the Bayesian viewpoint and show how thi...
Josef Kittler
CF
2007
ACM
14 years 3 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
ICASSP
2011
IEEE
13 years 2 months ago
Compressed classification of observation sets with linear subspace embeddings
We consider the problem of classification of a pattern from multiple compressed observations that are collected in a sensor network. In particular, we exploit the properties of r...
Dorina Thanou, Pascal Frossard