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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
14 years 2 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
SIGSOFT
2010
ACM
13 years 7 months ago
Bridging gaps between developers and testers in globally-distributed software development
One of the main challenges in distributed development is ensuring effective communication and coordination among the distributed teams. In this context, little attention has been ...
Mark Grechanik, James A. Jones, Alessandro Orso, A...
SIGSOFT
2010
ACM
13 years 7 months ago
An effective dynamic analysis for detecting generalized deadlocks
We present an effective dynamic analysis for finding a broad class of deadlocks, including the well-studied lock-only deadlocks as well as the less-studied, but no less widespread...
Pallavi Joshi, Mayur Naik, Koushik Sen, David Gay
IMC
2005
ACM
14 years 3 months ago
Characterization and Measurement of TCP Traversal Through NATs and Firewalls
In recent years, the standards community has developed techniques for traversing NAT/firewall boxes with UDP (that is, establishing UDP flows between hosts behind NATs). Because...
Saikat Guha, Paul Francis
HCI
2007
13 years 11 months ago
Measuring User Experiences of Prototypical Autonomous Products in a Simulated Home Environment
Advances in sensor technology, embedded processing power, and modeling and reasoning software, have created the possibility for everyday products to sense the environment and pro-a...
Martijn H. Vastenburg, David V. Keyson, Huib de Ri...