1095 search results - page 20 / 219 » Measuring the Performance of Parallel Message-Based Process ... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
PDP
2006
IEEE
14 years 1 months ago
2006
IEEE
— The Parallel Resource-Optimal (PRO) computation model was introduced by Gebremedhin et al. [2002] as a framework for the design and analysis of efficient parallel algorithms. ...
SC
1995
ACM
13 years 11 months ago
1995
ACM
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
JSA
2010
13 years 2 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
IGARSS
2009
13 years 5 months ago
2009
The main purpose of this paper is to describe available (HPC)based implementations of remotely sensed hyperspectral image processing algorithms on multi-computer clusters, heterog...