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SBACPAD
2003
IEEE
102views Hardware» more  SBACPAD 2003»
14 years 1 months ago
Performance Analysis of DECK Collective Communication Service
Collective communication is very useful for parallel applications, especially those in which matrix and vector data structures need to be manipulated by a group of processes. This...
Rafael Ennes Silva, Delcino Picinin, Marcos E. Bar...
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
13 years 11 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
13 years 12 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
HPCC
2010
Springer
13 years 8 months ago
Parallel Computational Modelling of Inelastic Neutron Scattering in Multi-node and Multi-core Architectures
Abstract--This paper examines the initial parallel implementation of SCATTER, a computationally intensive inelastic neutron scattering routine with polycrystalline averaging capabi...
Michael T. Garba, Horacio González-Vé...
SIPS
2007
IEEE
14 years 2 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...