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ICCD
2004
IEEE
158views Hardware» more  ICCD 2004»
14 years 4 months ago
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Z...
HPCA
2011
IEEE
12 years 11 months ago
Architectural framework for supporting operating system survivability
The ever increasing size and complexity of Operating System (OS) kernel code bring an inevitable increase in the number of security vulnerabilities that can be exploited by attack...
Xiaowei Jiang, Yan Solihin
CAMP
2005
IEEE
14 years 1 months ago
Development of a Bit-Level Compiler for Massively Parallel Vision Chips
Abstract— An image sensor in which each pixel has a processing element is called a vision chip. The vision chip can perform real-time visual processing at a high frame rate of 10...
Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa,...
PDPTA
2010
13 years 5 months ago
A Novel Computation-to-core Mapping Scheme for Robust Facet Image Modeling on GPUs
Though the GPGPU concept is well-known in image processing, much more work remains to be done to fully exploit GPUs as an alternative computation engine. The difficulty is not refo...
Seung In Park, Yong Cao, Layne T. Watson
MAM
2007
113views more  MAM 2007»
13 years 7 months ago
A reconfigurable computing framework for multi-scale cellular image processing
Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. Thes...
Reid B. Porter, Jan R. Frigo, Al Conti, Neal R. Ha...