Sciweavers

336 search results - page 30 / 68
» Memories of bug fixes
Sort
View
ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
13 years 12 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
GECCO
2006
Springer
123views Optimization» more  GECCO 2006»
13 years 11 months ago
The parallel Nash Memory for asymmetric games
Coevolutionary algorithms search for test cases as part of the search process. The resulting adaptive evaluation function takes away the need to define a fixed evaluation function...
Frans A. Oliehoek, Edwin D. de Jong, Nikos A. Vlas...
TCSV
2002
89views more  TCSV 2002»
13 years 7 months ago
Reducing energy dissipation of frame memory by adaptive bit-width compression
Abstract--In this paper, we propose a new architectural technique to reduce energy dissipation of frame memory through adaptive bitwith compression. Unlike related approaches, the ...
Vasily G. Moshnyaga
JOCN
2010
80views more  JOCN 2010»
13 years 6 months ago
Corticosteroids Operate as a Switch between Memory Systems
■ Stress and corticosteroid hormones are known to affect learning and memory processes. In this study, we examined whether stress and corticosteroids are capable of facilitating...
Lars Schwabe, Hartmut Schächinger, E. Ron de ...
IPPS
2010
IEEE
13 years 5 months ago
Dynamic analysis of the relay cache-coherence protocol for distributed transactional memory
Transactional memory is an alternative programming model for managing contention in accessing shared in-memory data objects. Distributed transactional memory (TM) promises to alle...
Bo Zhang, Binoy Ravindran