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JSA
2008
91views more  JSA 2008»
13 years 8 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi
ISORC
2005
IEEE
14 years 2 months ago
Building Responsive TMR-Based Servers in Presence of Timing Constraints
This paper is on the construction of a fault-tolerant and responsive server subsystem in an application context where the subsystem is accessed through an asynchronous network by ...
Paul D. Ezhilchelvan, Jean-Michel Hélary, M...
USS
2008
13 years 11 months ago
Lest We Remember: Cold Boot Attacks on Encryption Keys
Contrary to popular assumption, DRAMs used in most modern computers retain their contents for several seconds after power is lost, even at room temperature and even if removed fro...
J. Alex Halderman, Seth D. Schoen, Nadia Heninger,...
ICS
2009
Tsinghua U.
14 years 3 months ago
Fast and scalable list ranking on the GPU
General purpose programming on the graphics processing units (GPGPU) has received a lot of attention in the parallel computing community as it promises to offer the highest perfo...
M. Suhail Rehman, Kishore Kothapalli, P. J. Naraya...
CODES
2007
IEEE
14 years 2 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling