117 search results - page 18 / 24 » Memory Access Schemes for Configurable Processors |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
PLDI
2004
ACM
14 years 1 months ago
2004
ACM
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
MICRO
1997
IEEE
13 years 12 months ago
1997
IEEE
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
CLUSTER
2008
IEEE
14 years 2 months ago
2008
IEEE
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...